This invention relates to integrated circuit devices, and more particularly to the pass-gate structures that may be used in such devices.
One of the most ubiquitous structures within an integrated circuit device is the single-transistor passgate, which is commonly used to implement (either singly or in combination with other circuits) switches, multiplexers, logic functions (e.g., pass transistor logic), and gating mechanisms for tristatable circuits (e.g., buffers and drivers). In some integrated circuit devices, single-transistor passgate structures may account for a significant portion of the circuitry; for example, in the case of programmable logic devices, single-transistor passgates are used extensively throughout the device as part of the programmable interconnection circuitry.
The operation of a typical single-transistor passgate may be succinctly illustrated by a description of an NMOS passgate (analogous principles of operation, as understood by one skilled in the art, would apply for a PMOS passgate). Depending on whether the potential difference between its gate terminal, VGATE, and its source terminal, VSOURCE, exceeds the threshold voltage, VT, a NMOS passgate acts as an “open” or a “closed” switch. (As is well-known in the art, there is no physical difference between the “source” and “drain” terminals of a MOS device; the source terminal of a NMOS transistor is the terminal having the lower voltage.) When VGATE−VSOURCE is less than VT, the NMOS passgate is in the “cutoff” state, thereby acting as an “open” switch; when VGATE−VSOURCE is greater than VT, the NMOS passgate is in the conduction state, thereby acting as a “closed” switch.
As is well-known in the art, VT is not a discrete value for an MOS transistor; it may be considered a range of values that is influenced by a variety of second-order effects, such as substrate bias and subthreshold conduction. However, in order to simplify the illustration of the principles of the present invention, VT will be discussed herein as if it is a discrete value rather than a range of values.
With the current trend in scaling down device geometries (e.g., 0.18 μm process down to 0.13 μm, 90 nm, and lower) and the consequent use of ever-lower operating voltages (e.g., supply voltages, bias voltages, etc.), which are nearing levels comparable to VT, the ability of transistor passgate structures to function at relatively high speeds while at the same time minimizing leakage current is a difficult design hurdle to overcome.
Moreover, this trend of smaller device geometries and consequent use of lower operating voltages is creating a design tradeoff between speed (e.g., response time for the passgate transistor to turn ON) and leakage current (e.g., the current that passes through the passgate transistor when turned OFF) that was not previously experienced with larger device geometries and the consequent use of higher operating voltages. That is, if conventional design techniques are applied to smaller device geometries, high speed passgate operation is accompanied with high leakage current, whereas low leakage current is accompanied with low speed passgate operation. High leakage current is undesirable because it results in excess heat, power loss, and poorer performance.
Another problem associated with shrinking geometries is the consequent use of lower operating voltages. This lower operating voltage is typically a nominal voltage supplied to the integrated circuitry, and may be insufficient for certain circuitry, such as configurable memory cells (e.g., SRAM) within the integrated circuitry, to operate properly. For example, as the supply voltage decreases, the soft-error-rate increases because the critical charge needed to flip the cells (from one logic state to another) is reduced.